cell

Keys under a cell entry may be omitted by instead specifying them in under settings.cell_defaults. CharLib automatically merges any key-value pairs from settings.cell_defaults into each cell entry prior to characterization. If any key appears under both settings.cell_defaults and under a cell entry, the value in the cell entry overrides the default.

Required keywords:

netlist, models, functions, data_slews, loads

Allowed keywords:

area, clock, clock_slews, data_slews, enable, functions, hold_time_range, inputs, loads, models, netlist, outputs, pairs, plots, reset, set, setup_time_range, state

area

The physical core area occupied by the cell layout. Often given in square microns or gate equivalents. See Section 5.1.2 of the Liberty User Guide, Vol. 1 for details and examples.

type:

float or int

default:

0.0

clock

The clock pin name and trigger type, in the format <trigger> <name>. For edge-sensitive devices, trigger should be posedge or negedge. For level-sensitive devices, trigger may be not or omitted altogether. (For example: posedge CLK or negedge CKB)

type:

string

pattern:

^(posedge|negedge)[ ]*[a-zA-Z0-9_]+

clock_slews

A list of clock slew rates to characterize. The cell must have a clock pin in order to use this parameter. Unit is specified by settings.units.time.

type:

array

Every element of clock_slews is:

type:

float or int

data_slews

A list of input pin slew rates to characterize. Unit is specified by settings.units.time.

type:

array

Every element of data_slews is:

type:

float or int

enable

The enable pin name and trigger type, in the format <trigger> <name>. For edge-sensitive devices, trigger should be posedge or negedge. For level-sensitive devices, trigger may be not or omitted altogether. (For example: not CLK or GE)

type:

string

pattern:

^(not |())[ ]*[a-zA-Z0-9_]+

functions

A list of verilog functions describing each output as logical function of inputs. Input and output names must match ports names in the spice subcircuit.

type:

array

Every element of functions is:

type:

string

hold_time_range

A list containing the upper and lower bound to be used when characterizing hold time.

type:

array

Every element of hold_time_range is:

type:

float or int

inputs

A list of input pin names as they appear in the cell netlist. If present, used to verify function inputs.

type:

array

Every element of inputs is:

type:

string

loads

A list of output capacitive loads to characterize. Unit is specified by settings.units.capacitive_load.

type:

array

Every element of loads is:

type:

float or int

models

A list of paths to the spice models for transistors used in this cell’s netlist. If omitted, CharLib assumes each cell has no dependencies. * Using the syntax path/to/file will result in .include path/to/file in SPICE simulations. * Using the syntax path/to/dir will allow CharLib to search the directory for subcircuits used in a particular cell and include them using .include path/to/dir/file. * Using the syntax path/to/file section will result in .lib path/to/file section in SPICE simulations.

type:

array

Every element of models is:

type:

string

netlist

The path to the spice file containing the netlist for this cell.

type:

string

outputs

A list of output pin names as they appear in the cell netlist. If present, used to verify function outputs.

type:

array

Every element of outputs is:

type:

string

pairs

A list of pairs of pins to treat as differential pairs. Pairs must be listed in the format <noninverting_pin> <inverting_pin>.

type:

array

Every element of pairs is:

type:

string

plots

A string (or list of strings) specifying which plot(s) to show for this cell.

May satisfy any of the following definitions:

0

const:

all

1

const:

none

2

const:

io

3

const:

delay

4

type:

array

Every element of 4 is:

type:

string

reset

The name and trigger type of the cell’s reset pin, in the format {TRIGGER_FORMAT} (for example: negedge RN defines an active-low asynchronous reset pin).

type:

string

pattern:

^(posedge|negedge|not|!|())[ ]*[a-zA-Z0-9_]+

set

The name and trigger type of the cell’s set pin, in the format <trigger> <name>. For edge-sensitive devices, trigger should be posedge or negedge. For level-sensitive devices, trigger may be not or omitted altogether. (for example: not SN defines an active-low synchronous set pin).

type:

string

pattern:

^(posedge|negedge|not|!|())[ ]*[a-zA-Z0-9_]+

setup_time_range

A list containing the upper and lower bound to be used when characterizing setup time.

type:

array

Every element of setup_time_range is:

type:

float or int

state

A list of feedback paths which encode state in a sequential cell. Paths should be specified as <internal node> = <output pin>.

type:

array

Every element of state is:

type:

string